August 10, 2022

Samsung is rumored to start mass production of 3nm chips next week

Currently, only two independent foundries are capable of manufacturing advanced chips. The companies are TSMC and Samsung Foundry. Independent foundries take chip designs created by other companies and build the actual chips from that design. Both TSMC and Samsung are working on building chips using their 3nm process nodes. The smaller the process node used, the greater the number of transistors found inside a chip.

Samsung is rumored to announce mass production of 3nm chips as early as next week

This is important because the more transistors used in a chip, the more powerful and power efficient that chip can be. Every two years or so, the process node becomes smaller and more transistors fit into an integrated circuit. It’s the famous “Moore’s Law” you’ve heard of, named after Intel and Fairchild co-founder Gordon Moore. Remember that this is not a real law and as smaller and smaller components are built, this “observation” can no longer be fully counted towards doubling the number of transistors every two years.

Yet over time, you can see how “Moore’s Law” has predicted the incredible increase in processing capabilities over the years. Take the iPhone X, released in November 2017, powered by the Apple A10 Bionic chipset. The latter carried 4.3 billion transistors in each chip. Now let’s move on to the 2021 iPhone 13 series which sports the A15 Bionic chipset. The A15 Bionic contains 15 billion transistors, up 27.1% from the 11.8 billion transistors used by the A14 Bionic chip.

So now Samsung and TSMC are battling for supremacy in third-party chip building. TSMC is number one in most metrics and its customer list includes leading companies such as Apple (its number one customer), MediaTek, Nvidia, Qualcomm and others. But it seems, according to ExtremeTech, which Samsung will soon beat TSMC by launching mass production of chips made using its 3nm process node next week with TSMC starting 3nm mass production later this year.
Additionally, Samsung is going to use a new transistor structure on its 3nm chips called GAA or gate-all-around. With this structure, current flow is controlled by gates that contact the transistor on all four sides. TSMC will continue to use the FinFET structure that has been in place since the launch of the 22nm process node. TSMC will finally phase out FinFET for GAA when it starts shipping 2nm chips in 2026.

Samsung’s GAA design is called a Multi-Bridge Channel Field Effect Transistor (MBCFET), also known as a nanowire. It is one of only two all-around gate designs currently available with the second known as GAAFET or nanowire.

The report cites a major Korean news agency as saying that Samsung is expected to make a major announcement about its 3nm chip production soon. He also notes that switching to FinFet’s gate-all-around will reduce a chip’s area by 45% to help deliver a 30% performance increase while reducing power consumption by 50%. However, there is a big problem. Samsung reportedly achieved efficiencies of just 10% to 20% at 3nm, meaning the vast majority of its wafer-cut 3nm die arrays couldn’t pass quality control.

In February, a report indicated that Samsung’s yield on 4nm production was only 35%, causing Samsung to lose some business from chip designer Qualcomm. The latter would have transferred some of these orders to TSMC. However, if Samsung Foundry is about to announce the start of High Volume Manufacturing (HVM) at the 3nm process node, it could be concluded that Samsung Foundry has improved its performance by 3nm.
Speaking of 3nm, Digitimes reported that major TSMC customers such as AMD, Apple, Broadcom, Intel, MediaTek, Nvidia and Qualcomm have started lining up for 3nm capability. And next on the horizon, of course, is the 2nm process node that TSMC and Samsung are working on. Another name is expected to join TSMC and Samsung on the list of top foundries. Intel chief executive Pat Gelsinger has announced that the US company will take over process leadership from Samsung and TSMC by 2025.