Samsung announced on Thursday that its 3GAE (3nm-class gate-all-around early) manufacturing method is set to begin high-volume production this quarter (meaning within weeks). Not only is it the first 3nm class manufacturing method in the industry, it is also the first node to incorporate all-around gated field-effect transistors (GAAFETs).
Samsung Foundry’s 3GAE process technology is the company’s first to use GAA transistors, which Samsung calls multi-bridge channel field-effect transistors (MOSFETs).
The company has made many claims when describing its 256MB GAAFET SRAM chip developed with its 3GAE technology. Samsung claims the technique will result in a 30% performance improvement, a 50% reduction in power consumption, and up to an 80% increase in transistor density (including a mix of logic and SRAM). However, it remains to be seen how Samsung’s actual mix of performance and power consumption would play out.
About three years ago, Samsung unveiled its 3GAE and 3GAP nodes
Compared to the currently used FinFETs, GAAFETs in principle have many advantages. The channels of the GAA transistors are horizontal and flanked by gates. GAA channels are created by epitaxy and selective material removal, allowing designers to fine-tune them by changing the channel width of the transistor. Wider channels provide better performance, while narrower channels provide less power.
Such precision reduces transistor leakage current (i.e. reduces power consumption) and variability in transistor performance (provided everything is working correctly), resulting in lead times faster, faster time to market and higher returns. According to a recent Applied Materials presentation, GAAFETs have the potential to reduce cell space by 20-30%.
Recently announced high-vacuum Integrated Materials Solution (IMS) technologies have been applied to solve a major problem in GAA transistor fabrication: the deposition of multilayer gate oxides and metal gate stacks through the channels in the limited space provided. Applied Materials’ first new IMS technique uses integrated steps of atomic layer deposition (ALD), heating, plasma processing and metrology to fabricate a thinner 1.5 angstrom gate oxide. Dipole engineering and some ALD stages are combined in the metal gate IMS.
As an “early” 3nm class manufacturing technology, Samsung’s 3GAE will primarily be used by Samsung LSI (Samsung’s chip development arm) and perhaps one or two of SF’s other alpha customers.
Expect 3GAE technology to be widely used, assuming the yields and performance of these products meet expectations, given that Samsung’s LSI and other early SF consumers prefer to create chips in very large quantities. volumes.
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